Title :
A double layer metal CHMOS III technology
Author :
Smith, R.J. ; Sery, G. ; McCollum, J. ; Orton, J. ; Mantha, B. ; Smudski, J. ; Chi, T. ; Smith, S. ; Dishaw, J.P. ; Kokkonen, K.
Author_Institution :
Intel Corporation, Livermore and Santa Clara, CA
Abstract :
A high-performance CMOS technology (CHMOS III) utilizing 1.5 micron lithorgraphy, p-well processing, and two layers of metal has been developed. Transistor performance is obtained using 250 angstrom gate oxide and 1.0 micron typical electrical channel lengths for gate delays of less than 250 picoseconds. Transistor reliability is insured using a lightly doped drain (LDD) feature and latch up sensitivity is minimized at high layout density by using epitaxial silicon on an N+ substrate. Both high speed and low power capabilities of the technology have been demonstrated by the successful fabrication of two 16K SRAMs. The technology is ideally suited for VLSI random logic design and will be used for next generation 32 bit micro-processor production.
Keywords :
CMOS logic circuits; CMOS technology; Delay; Logic design; Routing; Silicon; Substrates; Transistors; Very large scale integration; Voltage;
Conference_Titel :
Electron Devices Meeting, 1984 International
DOI :
10.1109/IEDM.1984.190640
