DocumentCode
3556206
Title
Multilevel interconnection technology
Author
Ghate, P.B.
Author_Institution
Texas Instruments, Dallas, Texas
Volume
30
fYear
1984
fDate
1984
Firstpage
126
Lastpage
129
Abstract
Multilevel interconnections for both bipolar and MOS VLSI circuits, and the associated materials/process problems are reviewed. The application of barrier layered based double-level metal to bipolar and CMOS gate array device is illustrated. The potential for "designed-in" reliability for VLSI interconnects with proper attention to current density design rules and material selection will be discussed.
Keywords
Circuit optimization; Conducting materials; Conductive films; Conductivity; Current density; Fabrication; Integrated circuit interconnections; Materials reliability; Silicon; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1984 International
Type
conf
DOI
10.1109/IEDM.1984.190659
Filename
1484430
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