Title :
Multilevel interconnection technology
Author_Institution :
Texas Instruments, Dallas, Texas
Abstract :
Multilevel interconnections for both bipolar and MOS VLSI circuits, and the associated materials/process problems are reviewed. The application of barrier layered based double-level metal to bipolar and CMOS gate array device is illustrated. The potential for "designed-in" reliability for VLSI interconnects with proper attention to current density design rules and material selection will be discussed.
Keywords :
Circuit optimization; Conducting materials; Conductive films; Conductivity; Current density; Fabrication; Integrated circuit interconnections; Materials reliability; Silicon; Very large scale integration;
Conference_Titel :
Electron Devices Meeting, 1984 International
DOI :
10.1109/IEDM.1984.190659
