Buried isolation capacitor (BIC) cell for megabit MOS dynamic RAM

A new one-transistor, one-capacitor MOS dynamic RAM cell structure called a Buried Isolation Capacitor (BIC) cell has been developed for future 4M bit and beyond VLSI memory devices. Basic concept of the new cell structure is mergence of capacitor and isolation region into a buried capacitor formed in a trench. Sidewall of the trench and the poly Si buried within the trench form two plates of the capacitor. The^IIB⁺-implanted p-type layer at the bottom of the trench acts as an isolation region between adjacent cells. The devised new structure, combined with submicron lithography, realizes extremely small cell size about 7 µm². This enables reasonable size 4M bit DRAM chip about 60 mm². Process technologies and experimental results on the electrical characteristics of the new cell structure are described.