Trench capacitor leakage in Mbit DRAMs

The limitations on trench capacitors imposed by leakage mechanisms in high density DRAMs has been studied through simulations. The primary purpose of the work has been to investigate all possible leakage mechanisms and to determine the optimum substrate doping profile for which the trench capacitor leakage is sufficiently suppressed. The effect of all relevant structural, process and electrical parameters on the required substrate doping profile is also fully investigated. The substrate doping density at which impact ionization causes avalanche breakdown at the trench capacitor junction has also been estimated. It is shown that for trench spacing of 0.75 µm or more. an intermediate range of substrate doping concentrations can always be found for which both the trench leakage and the junction breakdown can be avoided.