Reduced n+/p+-spacing with high latchup hardness in self-aligned double well CMOS technology

Latchup in CMOS circuit with an epitaxial layer originates from short channel effects of the parasitic field oxide transistors and from voltage drops on shunt resistances. The short channel behaviour of the field oxide transistors was improved by reducing the p-well depth and modifying the local oxidation step for the well generation. By laser scanning microscope it is shown that for the conventional well latchup firing occurs at the bulges of the well boundary. Using the shallow well the charge compensated region at the well boundary and thereby the latchup sensitive bulges are eliminated. With shallow p-well the shunt resistances are reduced by diminished out-diffusion of the heavily doped n⁺-substrate and by feasible use of a thinner epi-layer. These measures enable to reduce the critical n⁺/p⁺-spacing of adjacent n-and p-channel transistors from 12 µm to 6µm without loosing latchup hardness.