A fine-line CMOS technology that uses p+polysilicon/silicide gates for NMOS and PMOS devices

We have developed a fine-line CMOS technology that uses a single-type, p⁺polycide (polysilicon/silicide) gate for both NMOS and PMOS transistors. This approach eliminates the problems encountered when using n- and p-type polysilicon gate for NMOS and PMOS transistors that have a common polycide gate. For the n- and p-type polysilicon gates under silicide structure, it has been found that extremely rapid lateral impurity diffusion occurs in the TaSi2upper layer of the polycide gate structure Such impurity diffusion alters the work functions of the adjacent NMOS and PMOS devices. With p⁺-polycide gates for both types of devices, the PMOS device is a "surface-channel" type, and the NMOS device is a (normally off) "buried-channel" type The PMOS device is less prone to punchthrough at short channel lengths than the NMOS device; however, the NMOS device performance benefits from the mobility enhancement of the buried-channel structure. We will highlight here the relativity advantages and disadvantages of the surface-and buried-channel NMOS devices. We describe the I-V characteristics of p⁺-polycide gate NMOS and PMOS transistors having 175Å thick gate oxide, threshold voltages of ±0.7V and electrical channel lengths of 1.0µm.