High performance subhalf-micrometer P-channel transistors for CMOS VLSI

We have designed, modeled, and fabricated subhalf-micrometer PMOS transistors. Two-dimensional process and device modeling were extensively exercised to determine the critical process parameters for device optimization. Buried-channel behavior of the p-channel FET has been analyzed. The effect of A lightly-doped drain (LDD) structure on punch-through voltage was studied. P-channel FETs with physical gate length as short as 0.3 µm were fabricated using e-beam lithography, LDD structure, and silicided source/drains. The experimental devices show high transconductance and long-channel characteristics.