Design of an E2PROM memory cell less than 100 square microns using 1 micron technology

In this paper, the design of a state of the are E²PROM memory cell is presented. This memory cell is being incorporated in a third generation electrically erasable non-volatile memory technology based on 1 µm lithography. The 1 µm lithography is being used aggressively in the design of the memory cell to achieve the highest feature density. The memory cell is 13.5 µm in Y dimension and 7 µm in X dimension. The basic philosophy of the design is the maximization of coupling ratio, both in program and erase. This allows the use of a thicker tunnel oxide to give the highest yield and reliability. The tunnel oxide area is defined by two masking steps instead of one in competitive designs to minimize the drain capacitance, giving higher erase coupling ratio and thus a larger window. It will be shown that this is a very solid and reliable cell that will be used in high density E²PROMs.