Trench isolation prospects for application in CMOS VLSI

This paper reviews recent progress made and problems encountered in the development of deep trench isolation for CMOS integrated circuits, the advantages and disadvantages of this technique relative to more conventional planar isolation technology are discussed, with consideration given to manufacturability, latch-up suppression, and parasitic sidewall channel formation. It is concluded that the near term (next 3 to 5 years) is unlikely to see widespread use of trench isolation in CMOS, while longer term use will be primarily for niche (cost-insensitive) applications.