DocumentCode :
3556349
Title :
N- and p-well process compatibility in a 1 µm-CMOS technology
Author :
Jacobs, E.P. ; Takacs, D. ; Schwabe, U.
Author_Institution :
Siemens AG, München, FRG
fYear :
1984
fDate :
9-12 Dec. 1984
Firstpage :
642
Lastpage :
646
Abstract :
A 1 µm CMOS concept for 5 V supply-voltage with 22 nm gate oxide and a pure TaSi2gate is presented which allows to realize a n-well- and a p-well-process with widely compatible process flow. Starting in either case from 20 Ωcm epitaxial material on 0.02 Ωcm substrate the process uses equal well depths and identical low well dopant concentrations. Charge carrier mobilities have been found identical in both process concepts. N-channel low-level breakdown voltage is independent of the process concept used. Also independent of the well type the specific junction capacitances inside the well are nearly identical, outside the well typically different. Using ring oscillators with Leff=1.2 µm minimum propagation delays of 120ps for the p-well process and 190ps for the n-well process have been measured.
Keywords :
Auditory implants; Boron; Doping; Electric breakdown; Oxidation; Process design; Substrates; Surface resistance; Tellurium; Testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 1984 International
Conference_Location :
San Francisco, CA, USA
Type :
conf
DOI :
10.1109/IEDM.1984.190804
Filename :
1484575
Link To Document :
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