A highly reliable N-MOS process for one megabit dynamic random access memory

An n-channel MOS process has been developed to yield reliable one megabit dynamic RAMs. Main features of the process are as follows; * Adoption of epitaxial-growth wafer * Bird´s beak-reduced LOCOS isolation * Highly reliable memory cell capacitor with 10nm SiO2* Low resistivity TiSi2polycide gate electrode * Al-Si-Ti interconnection with low temperature planarization of the underlying layer * 1.2µm pattern formation by a 5:1 step and repeat aligner followed by the reactive ion etching A highly reliable 1M×1 dynamic MOS memory was successfully fabricated using these processes.