Characterization of As-P double diffused drain structure

In order to improve the source-drain gated breakdown and hot electron injection in submicron channel length MOSFET devices, an As-P double-diffused (DD) drain structure is implemented. The feasibility of this device is investigated, comparing it to conventional As only devices. Oxide sidewall spacers have been successfully fabricated to insure the formation of the lightly doped for region. The fabrication process is similiar to conventional gate processing except a conformal CVD-SiO2layer is deposited after polysilicon gate definition. This layer is then reactive ion etched to form the sidewall spacers. Extensive device characterization shows reduction of gate and substrate hot electron injection, overlap capacitance, and gated breakdown. Transconductance degradation is shown to be approximately 10% for the double-diffused device at an Leff = 1.0 µm when compared to the conventional device. However, modeled results of ring oscillator performance predict an overall performance improvement of 10% for the graded junction.