DocumentCode
3556420
Title
Hardware logic simulation by compilation
Author
Hansen, Craig
Author_Institution
MIPS Comput. Syst. Inc., Sunnyvale, CA, USA
fYear
1988
fDate
12-15 Jun 1988
Firstpage
712
Lastpage
715
Abstract
A behavioral and logic simulation system which uses extensive optimization and compilation techniques to obtain high performance is described. It incorporates data-flow analysis to optimize the evaluation of unordered assignment statements that define a hardware structure, and to extract clocking rules. An integral code generator produces efficient assembly code for three different machines, and an associated run-time library provides a flexible interactive debugging environment
Keywords
circuit analysis computing; logic CAD; optimisation; Terse; assembly code; compilation; data-flow analysis; hardware structure; integral code generator; interactive debugging environment; logic simulation system; optimization; unordered assignment statements; Arithmetic; Clocks; Computational modeling; Computer simulation; Equations; Hardware; High performance computing; Logic; Runtime; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1988. Proceedings., 25th ACM/IEEE
Conference_Location
Anaheim, CA
ISSN
0738-100X
Print_ISBN
0-8186-0864-1
Type
conf
DOI
10.1109/DAC.1988.14848
Filename
14848
Link To Document