Clock event suppression algorithm of VELVET and its application to S-820 development

Author

Takamine, Yoshio ; Miyamoto, Shunsuke ; Nagashima, Shigeo ; Miyoshi, Masayuki ; Kawabe, Shun

Author_Institution

Hitachi Ltd., Tokyo, Japan

fYear

1988

fDate

12-15 June 1988

Firstpage

716

Lastpage

719

Abstract

An advanced clock event suppression algorithm for high-speed logic simulation is described. A signal value, Cn, and a current clock (CC), which indicates the current status of clock signals, has been introduced to realize this algorithm. This algorithm suppresses about 60% of the total events, and eliminates 40% of CPU time. No overhead is needed to incorporate this algorithm using hardware support of VELVET (vectorized processing system for logic verification). Hitachi´s latest supercomputer S-820 has been developed using VELVET. The development period has been shortened to 3/4 that of the S-810.<>

Keywords

circuit analysis computing; digital computers; fault tolerant computing; logic testing; parallel machines; synchronisation; Hitachi; S-820 development; VELVET; clock event suppression algorithm; high-speed logic simulation; logic verification; supercomputer; vectorized processing system; Clocks; Computational modeling; Discrete event simulation; Hardware; Logic design; Logic testing; Supercomputers; Synchronization; Vector processors; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Design Automation Conference, 1988. Proceedings., 25th ACM/IEEE

Conference_Location

Anaheim, CA, USA

ISSN

0738-100X

Print_ISBN

0-8186-0864-1

Type

conf

DOI

10.1109/DAC.1988.14849

Filename

14849