Title :
A path selection algorithm for timing analysis
Author :
Yen, H.C. ; Ghanta, S. ; Du, H.C.
Author_Institution :
Dept. of Comput. Sci., Minnesota Univ., Minneapolis, MN, USA
Abstract :
Existing algorithms for timing analysis have difficulties when dealing with large designs. A novel algorithm for timing analysis is proposed that enumerates all the paths with delay greater than a given threshold. The execution time of the proposed algorithm is proportional to the number of paths generated, so it is suitable for large designs.<>
Keywords :
delays; logic design; logic testing; delay; execution time; large designs; logic design; path selection algorithm; timing analysis; timing verification; Algorithm design and analysis; Circuit faults; Computer science; Delay; Design automation; Design engineering; Digital systems; Logic; Production systems; Timing;
Conference_Titel :
Design Automation Conference, 1988. Proceedings., 25th ACM/IEEE
Conference_Location :
Anaheim, CA, USA
Print_ISBN :
0-8186-0864-1
DOI :
10.1109/DAC.1988.14850
