Title :
A sub-100 picosecond bipolar ECL technology
Author :
Vora, M. ; Ho, Y.L. ; Bhamre, S. ; Chien, F. ; Bakker, G. ; Hingarh, H. ; Schmitz, C.
Author_Institution :
Fairchild Research Center, Palo Alto, CA
Abstract :
A fully Self-Aligned Polysilicon bipolar transistor with Trench structure (SAPT) has been developed for its application in high-performance ECL circuits. An ECL gate delay of 80 ps was obtained with a transistor designed with 2 micron lithography (1.5 um emitter). This new transistor structure with two levels of polysilicon and trench technique for isolation promises to become very attractive for giga-bit digital systems.
Keywords :
Bipolar transistor circuits; Bipolar transistors; Boron; Capacitance; Delay; Digital systems; Dry etching; Lithography; Plasma applications; Silicon;
Conference_Titel :
Electron Devices Meeting, 1985 International
DOI :
10.1109/IEDM.1985.190884
