DocumentCode :
3556451
Title :
GaAs FET with a degenerate semiconductor gate
Author :
Umemoto, Y. ; Takahashi, S. ; Ono, Y. ; Hashimoto, N.
Author_Institution :
Hitachi, Ltd., Tokyo, Japan
Volume :
31
fYear :
1985
fDate :
1985
Firstpage :
86
Lastpage :
89
Abstract :
A new GaAs FET structure has been proposed and examined experimentally in which the gate material is degenerate p-Al0.3 Ga0.7 As fabricated directly on to a p-type layer of undoped semi-insulating GaAs substrates. Obtained transconductance was 207mS/mm under the gate bias of 2V for the gate length of 
m and the onset voltage of the gate leakage current was 0.5-0. 6V higher than that of MESFETs. These characteristics were explained by the presence of an n-type inversion layer located at p-AlGaAs/p-GaAs interface. Temperature dependence of the drain current leads to a conclusion that the Fermi level was pinned at the interface states 0.475eV above the valence band.
m and the onset voltage of the gate leakage current was 0.5-0. 6V higher than that of MESFETs. These characteristics were explained by the presence of an n-type inversion layer located at p-AlGaAs/p-GaAs interface. Temperature dependence of the drain current leads to a conclusion that the Fermi level was pinned at the interface states 0.475eV above the valence band.Keywords :
FETs; Gallium arsenide; Interface states; Leakage current; MESFETs; Semiconductor materials; Substrates; Temperature dependence; Transconductance; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 1985 International
Type :
conf
DOI :
10.1109/IEDM.1985.190898
Filename :
1485448
Link To Document :
