A self-aligned short process for insulated gate transistors

A new IGT process which implements a self-aligned short is proposed and demonstrated experimentally. The salient feature of the new process is the placement of a poly-Si plug to define the diffusion window of the P+ short. Similar forward conduction characteristics and tradeoffs with turn-off time were obtained for these self-aligned short IGT´s when compared to conventional IGT´s with nonself-aligned shorts. With a resistive load and no external gate resistor, dynamic latching current was seen to increase with increasing P+ diffusion depth and electron dosage.