Relief of hot carrier constraint on submicron CMOS devices by use of a buried channel structure

Hot carrier effects of submicron buried channel NMOS devices with a LDD structure have been investigated because of a need to realize high performance future VLSI structure. The stress experiments show that the buried channel device is resistant to hot carrier effects and give a relief of hot carrier constraint for the scaled down devices. The improvement in hot carrier degradation is attributed to the deeper and broader current path in the buried channel structure. Dependences of the hot carrier effect and the short channel effect on the channel junction depth are discussed. These results help select the most promising buried channel CMOS structure for high-speed and high-reliability future VLSI.