Dynamic cross-coupled bitline content addressable memory cell for high density arrays

This paper describes the design of a novel dynamic Content Addressable Memory (CAM) cell suitable for high density arrays on the order of 64K bits. The proposed cell is capable of storing three internal states; \´1\´, \´0\´ and "don\´t care" (MASK). The cell consists of five NMOS transistors of which four are used to store and access data and one is used as a diode to isolate current paths. Charge is stored on the gate of a transistor which results in non-destructive current driven Read and Match operations and increases the charge storage time leading to higher reliability and improved immunization to alpha particles. Using 2µm design rules, buried contacts, single level metal, and low resistance polycide lines results in a CAM cell 25µm × 22µm which is comparable to 64K bit static RAM cell areas. The CAM cell was sucessfully fabricated using a 4µm NMOS process and its operation was confirmed with a 2 × 3 bit array.