1/4 µm CMOS isolation technique with sidewall insulator and selective epitaxy

A new CMOS isolation technique has been developed, wherein devices are isolated by quarter-micrometer-thick insulator films. This technique is supported by two key processes. One is to form insulator films on trench sidewalls, which are shaped perpendicularly to the substrate plane. The other is to refill the trenches with selectively grown single crystal silicon. CMOS devices are composed of n-channel MOSFETs fabricated on the p-type substrate and p-channel MOSFETs fabricated on the selective epi-layer, which are isolated with the sidewall insulator films. It was experimentally ascertained using this technique that the decrease in isolation distance was limited by parasitic MOS operation.