DocumentCode :
3556545
Title :
High speed BiCMOS VLSI technology with buried twin well structure
Author :
Watanabe, A. ; Ikeda, T. ; Nagano, T. ; Momma, N. ; Nishio, Y. ; Tamba, N. ; Odaka, M. ; Ogiue, K.
Author_Institution :
Hitachi Ltd., Ibaraki, Japan
Volume :
31
fYear :
1985
fDate :
1985
Firstpage :
423
Lastpage :
426
Abstract :
Bipolar transistors of high cut off frequency ( 
GHz) and small size have been fabricated on the same chip with a standard CMOS using the buried twin well structure. 1.3 µm LDD CMOS FETs were formed in the thin epitaxial layer(1-1.5µm) with the buried twin well, without degrading the device characteristics of the MOS FET. Ring oscillators of the BiCMOS gate have been fabricated. A 0.4ns gate delay time at 0.6pF and 3.5 times larger driveability than that of the same area CMOS gate were obtained.
GHz) and small size have been fabricated on the same chip with a standard CMOS using the buried twin well structure. 1.3 µm LDD CMOS FETs were formed in the thin epitaxial layer(1-1.5µm) with the buried twin well, without degrading the device characteristics of the MOS FET. Ring oscillators of the BiCMOS gate have been fabricated. A 0.4ns gate delay time at 0.6pF and 3.5 times larger driveability than that of the same area CMOS gate were obtained.Keywords :
BiCMOS integrated circuits; Bipolar transistors; CMOS process; CMOS technology; Degradation; Epitaxial layers; FETs; Fabrication; Impurities; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 1985 International
Type :
conf
DOI :
10.1109/IEDM.1985.190991
Filename :
1485541
Link To Document :
