Static and transient latch-up hardness in N-well CMOS with on-chip substrate bias generator

Theoretical considerations and experimental results of the influence of an on-chip substrate bias generator on static and transient latch-up hardness in n-well CMOS are presented. The current drive capability of the VBBgenerator is limited, its internal resistance is operating point dependent. If the VBBgenerator is not capable to sink the static and the time averaged transient substrate currents, localized forward biasing of the substrate takes place, thus triggering latch-up. A special clamp circuit was used for limiting the forward substrate bias below the value capable to trigger the parasitic SCR. Using such clamping techniques the latch-up hardness with on-chip bias generator can significantly be improved during power-up and in normal operation mode.