Floating well CMOS and latchup

The operation of CMOS devices in an electrically floating well is considered. The impetus for this study is the potential reduction of silicon area consumption and wiring complexity attainable when the need for well contacts is eliminated. Experimental P-channel transistor characteristics are presented, for both the floating and non-floating well cases; consideration extends to FET device characteristics, subthreshold behavior, as well as junction leakage and breakdown voltage. Results indicate that transistor operation is not significantly affected when the well is electrically floated. Latchup hardness is somewhat but not excessively degraded when the well is floated, and is explained by means of a simple holding voltage model. It is shown that increased source (emitter) resistance may offset this degradation.