Optimum crystallographic orientation of submicron CMOS devices

The dependence of submicron-channel CMOS performance on surface orientation is examined for LDD devices at both 300 K and 77 K. Special emphasis is placed on determining the optimum crystalline plane for a CMOS operating at cryogenic temperatures (CRYO-CMOS). In n-channel MOS transistors, the difference in saturation current among various crystalline orientations decreases as the channel length is reduced. In contrast, the saturation current of p-channel devices reaches a maximum value on the