Buried storage electrode (BSE) cell for megabit DRAMs

The structure, fabrication and electrical characteristics of a new one-transistor one-capacitor MOS memory cell for megabit DRAMs are presented. In the cell, a buried polysilicon electrode, refilled into a capacitor trench and connected to a transfer MOSFET electrode, serves to store the signal charge, while the heavily doped substrate of a p/p⁺⁺epi wafer serves as the capacitor plate. Because of its inherent punchthrough-free nature and high immunity against alpha-particle soft errors, the cell is suitable for high density integration. A test element group of the cell was fabricated with 0.8um design rule yielding memory cell size of 8.8um²and storage capacitance of 35fF. Basic memory cell operation was demonstrated successfully, where the charge retention time of more than 2 sec was observed. The interference between the adjacent cells separated by 0.8um was confirmed to be negligible.