Selective CVD tungsten via plugs for multilevel metallization

Use of selective metal CVD tungsten is shown to be a viable method of filling small via holes in multilevel metal integrated circuits. The method specifically described utilizes Mo/TiW as the first level metal (M1); a planarized interlevel dielectric; straight via holes filled with tungsten and A1 second level metal (M2). This methodology solves the problems of variable via depth encountered in integrated circuits when interlevel dielectrics are planarized and whenever design rules are utilized which allow for stacked and unstacked via connections to underlying features at widely varying topological height. The method also provides a means of greatly reducing metal interconnection pitch. It also eliminates the necessity for tapering via or contact holes usually utilized to obtain suitable metal coverage within the holes.