A 3.3-ps Josephson or gate with Niobium junctions

In this paper, we describe the design, fabrication, and evaluation of a Josephson logic gate with all-niobium junctions. Recently, we reported a 4.2-ps Modified Variable Threshold Logic (MVTL) OR gate. We redesigned the MVTL gate, in order to confirm the feasibility of its use as an ultra high speed gate. The minimum diameter of the Nb/AiOx/Nb junctions was reduced from 2.5 µm to 2.0 µm to decrease the junction capacitance. Resistance and inductance values were also optimized to attain high-speed operation. We evaluated an OR gate with a 5- stage gate chain by means of the Josephson sampling technique. The measured minimum gate delay was 3.3 ps/gate for a power consumption of 9.1 µW/gate.