Trench transistor cell with self-aligned contact (TSAC) for megabit MOS DRAM

A new one-transistor, one-capacitor MOS dynamic RAM cell structure called a Trench Transistor Cell with Self-Aligned Contact (TSAC) has been developed for 4M bit and beyond VLSI memory devices. Basic concept of the new cell structure is shrinkage of the conventional trench capacitor cell using the following technologies; (1) Trench transistor as a transfer gate, and (2) Bit line contact, which is self-aligned to the word line. Superior immunity of the trench transistor from short and narrow channel effects, combined with marginless contact design capability, enables substantial reduction of the memory cell size. Adopting submicron design rule, the new cell realizes extremely small cell size below 9 µm². This enables reasonable size 4M bit chip, which can be encapsulated in a 300 mil DIP.