A novel isolation structure for SMARTpower ICs

This paper describes a new isolation technology for SMARTpower^TMdevices. The structure allows a vertical power device to be integrated with low voltage control circuitry. The new process utilizes etch, epi, and polishing techniques to isolate the power device. This method is compared to current methods of achieving isolation such as diffused junctions. The paper discusses the advantages of this "etch-refill" technique and related development issues are discussed. Finally, a SMARTpower^TMcircuit with BICMOS logic and a TMOS power FET output device was fabricated on etch-refill substrates and compared to a circuit which used the more conventional diffused isolation.