A versatile, high-performance, double-level-poly double-level-metal, 1.2-micron CMOS technology

We have developed an advanced CMOS technology for application in fast SRAMS, non-volatile memory, microprocessor and logic circuits. Features of the 1.2µm (gate and contact) double-level-poly, double-level-metal technology include a twin-well CMOS [1] structure in n- or p-type starting material, SILO isolation [2] for high packing density, 250 A thick gate oxide, 0.9µm-nominal-effective channel-length (Leff) NMOS devices with moderately lightly doped drains [3], optional LDD PMOS devices for high-voltage circuit applications, low-temperature-flow BPSG, a TiSi/TiN/Al contact and barrier metallurgy, and three-micron and four-micron first-and second-level-metal pitches respectively. Novel features of the technology include a single-mask dual-chanstop PMOS field-and-punch-through-implant scheme as well as disposable gate-sidewall spacers for LDD formation on CMOS devices. Reliability has been designed into the technology with emphasis on hot-carrier-protected transistors and metallization.