DocumentCode
3556731
Title
A high performance submicron CMOS process with self-aligned chan-stop and punch-through implants (Twin-Tub V)
Author
Chen, M.L. ; Leung, C.W. ; Cochran, W.T. ; Harney, R. ; Maury, A. ; Hey, H.P.W.
Author_Institution
AT&T Bell Laboratories, Allentown, P.A.
Volume
32
fYear
1986
fDate
1986
Firstpage
256
Lastpage
259
Abstract
An optimally designed process used for our fifth generation CMOS technology (Twin-Tub V) is described in this paper. This process has the inherent advantages of process simplicity, excellent transistor performance and latch-up resistance. A single level silicide and two level metal interconnect is also incorporated in this technology.
Keywords
Boron; CMOS process; CMOS technology; Etching; Hot carrier effects; Implants; MOS devices; Power supplies; Silicides; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1986 International
Type
conf
DOI
10.1109/IEDM.1986.191163
Filename
1486421
Link To Document