DocumentCode
3556787
Title
Self-aligned processes for the GaAs gate FET
Author
Baratte, H. ; La Tulipe, D.C. ; Knoedler, C.M. ; Jackson, T.N. ; Frank, D.J. ; Solomon, P.M. ; Wright, S.L.
Author_Institution
IBM T.J. Watson Research Center, Yorktown Heights, NY
Volume
32
fYear
1986
fDate
1986
Firstpage
444
Lastpage
447
Abstract
We have developed cold gate and refractory gate self-aligned processes for the GaAs-based SISFET. Using either of these approaches, we have demonstrated 0.7 µm gate length devices with near-zero threshold voltage, transconductance of 280mS/mm at 300K and 400mS/mm at 77K and low gate leakage. We have also fabricated 23-stage ring oscillators which yielded delays of 35ps/gate and speed-power products of 10fJ/gate at 300K.
Keywords
Annealing; Contact resistance; Etching; FETs; Gallium arsenide; Implants; Insulation; Ohmic contacts; Threshold voltage; Transconductance;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1986 International
Type
conf
DOI
10.1109/IEDM.1986.191215
Filename
1486473
Link To Document