Thermoelastic model of dislocations in wafers

The temperature and thermal stress distributions in regularly spaced circular wafers in a row in a furnace which has been used for semiconductor fabrication processes are investigated both theoretically and experimentally. A mathematical thermoelastic model is proposed to estimate the transient temperature and stress distributions in wafers of various sizes and of various row positions. The process conditions necessary to prevent defects (dislocations) are established by comparing the yield stress with the calculated stress resolved on the {111} planes in the directions. The results are in good agreement with experiments.