Ultra low specific on-resistance UMOS FET

This paper describes an improved UMOS FET with an ultra low specific on-resistance. This device utilizes a self-aligned process which permits closed spaced vertical trench gates with a unit cell of 6 µm. This allows for a remarkable increase of channel density and therefore, reduces the on-resistance per unit area significantly. Experimental devices have been fabricated, and a specific on-resistance of 1.2 Ω-cm², which is the lowest value ever reported, has been achieved.