DocumentCode :
3556852
Title :
The effects of SIPOS passivation on DC and switching performance of high voltage MOS transistors
Author :
Mukherjee, S. ; Chou, C.J. ; Shaw, K. ; McArthur, D. ; Rumennik, V.
Author_Institution :
Philips Laboratories, North American Philips Corporation, Briarcliff Manor, N.Y.
Volume :
32
fYear :
1986
fDate :
1986
Firstpage :
646
Lastpage :
649
Abstract :
For long term stability of high voltage NMOS transistors the application of a SIPOS passivation layer over the drift regions has been studied. This has been found to change the device characteristics both for steady state and switching. This paper describes the mechanism of interaction of the SIPOS layer and the drift region of the device and presents 2-dimensional simulation results together with experimental data. An analytical 1-dimensional model is outlined and shown to agree well with the 2-dimensional simulation results.
Keywords :
Analytical models; Circuit simulation; Conductivity; Ice; Laboratories; MOSFETs; Passivation; Silicon; Steady-state; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 1986 International
Type :
conf
DOI :
10.1109/IEDM.1986.191274
Filename :
1486532
Link To Document :
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