Impact of hot electron trapping on half micron PMOSFETs with p+poly Si gate

Hot carrier trapping effects have been studied on a half micron p⁺poly-Si gate PMOSFET which is the optimum device structure in future VLSI. The stress experiments show that the hot carrier-induced device degradation becomes appreciable even at supply voltage in half-micron VLSI because of the increase in avalanched hot electron trapping. From a detailed comparison of hot carrier effect at short stress time between PMOS and NMOS FETs, we have clarified the hot electron trapping mechanism for PMOS and NMOS FETs systematically. Though we need to pay attention to the hot carrier degradation of p⁺poly-Si gate PMOSFET, the p⁺poly-Si gate is an applicable technology to half-micron VLSIs.