Parasitic resistance characterization for optimum design of half micron MOSFETs

The parasitic resistance of source and drain regions has been investigated for optimum design of half micron MOSFETs operating at reduced supply voltage. For LDD structure, this resistance was found to be mainly determined by the spreading resistance in source and drain near channel edge. It was also clarified that the buried channel structure could reduce the parasitic resistance because the spreading resistance which comes from the current crowding in source and drain regions depends on the thickness of the current flow at channel region. To minimize above parasitic resistance, it is the key to achieve the steep impurity profile in LDD region and the deep spreaded current flow in buried channel structure. Optimally designated arsenic LDD and buried channel structure are effective to realize the reliable and low parasitic resistance structure.