A novel submicron LDD transistor with inverse-T gate structure

A novel submicron LDD transistor is demonstrated in which there is a thin extension of the gate polysilicon under the oxide sidewall-spacer giving the gate\´s cross section the appearance of an inverted letter T. The new inverse-T LDD (ITLDD) transistor features the self alignments of n^-LDD and n⁺source-drain implants to the inside and outside edge, respectively, of the IT gate structure. Optimum n^-LDD length for reducing the electric field in the channel region can be achieved by controlling the width of the oxide sidewall-spacer abutting the ledge of the IT-gate in a similar manner to a conventional LDD transistor. However, the "spacer-induced degradations" existing in a conventional LDD transistor are eliminated as a result of the self-aligned n⁺-to-gate feature in ITLDD. This allows the use of low n^-LDD dose for optimum channel electric field reduction and minimum post-implant drive-in for future VLSI compatibility. Submicron ITLDD transistor with improved transconductance and reliability has been achieved. The new ITLDD transistor offers a promising device structure for future VLSI applications.