DocumentCode :
3556974
Title :
A self-aligning polysilicon electrode technology (SPEL) for future LSIs
Author :
Misawa, Y. ; Homma, H. ; Sato, K. ; Momma, N.
Author_Institution :
Hitachi, Ltd., Ibaraki, Japan
Volume :
33
fYear :
1987
fDate :
1987
Firstpage :
32
Lastpage :
35
Abstract :
A Self-aligning Polysilicon ELectrode technology (SPEL) is proposed to realize future high performance LSIs. This technology, based on a preferential dry etching of a highly doped polysilicon, makes it possible to halve the contact region areas of MOS and bipolar transistors as compared to conventional ones. Additionally, reduction of parasitic capacitance and resistance are demonstrated for the former transistors.
Keywords :
Annealing; Bipolar transistors; Dry etching; Electrodes; MOS devices; MOSFETs; Metallization; Oxidation; Parasitic capacitance; Silicon;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 1987 International
Type :
conf
DOI :
10.1109/IEDM.1987.191340
Filename :
1487298
Link To Document :
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