Quasi-static simulation of hot-electron-induced MOSFET degradation under AC (pulse) stress

A substrate current model and a quasi-static hot-electron-induced MOSFET degradation model have been implemented in the Substrate Current and Lifetime Evaluator (SCALE). It is shown that quasi-static simulation is valid for a class of waveforms including those encountered in inverter-based logic circuits. The validity and limitations of the model are illustrated with experimental results. SCALE is linked to SPICE externally in a pre- and post- processors fashion to form an independent simulator. The pre-processor interprets the input deck, and requests SPICE to output the transient node voltages of the user-selected devices. The post-processor then calculates the transient substrate current and makes lifetime prediction.