DocumentCode
3556982
Title
Hot carrier aging in two level metal processing
Author
Chen, M.-L. ; Leung, C.-W. ; Cochran, W.T. ; Jain, S. ; Hey, H.P.W. ; Chew, H. ; Dziuba, C.
Author_Institution
AT&T Bell Laboratories, Allentown, PA
Volume
33
fYear
1987
fDate
1987
Firstpage
55
Lastpage
58
Abstract
This paper describes device degradation induced during processing steps often used in submicron CMOS multi-level metal technologies. D.C. stressed device aging is used to characterize process induced device degradation. The aging characteristics are degraded with certain types of second layer metal processing. Once the devices are capped with conventional SIN, there is no significant difference in the aging characteristics.
Keywords
Aging; CMOS process; CMOS technology; Degradation; Electron traps; Etching; Hot carriers; Silicon compounds; Stress; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1987 International
Type
conf
DOI
10.1109/IEDM.1987.191346
Filename
1487304
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