DocumentCode
3557064
Title
Process technologies for high density, high speed 16 megabit dynamic RAM
Author
Horiguchi, F. ; Nitayama, A. ; Hieda, K. ; Hamamoto, T. ; Tsuda, K. ; Sunouchi, K. ; Takenouchi, N. ; Aritome, S. ; Takato, H. ; Kimura, M. ; Yamabe, K. ; Nakase, M. ; Kamata, Y. ; Masuoka, F.
Author_Institution
Toshiba Corporation, Kawasaki, Japan
Volume
33
fYear
1987
fDate
1987
Firstpage
324
Lastpage
327
Abstract
This paper describes key points of submicron CMOS technologies for an experimental 16 Mbit DRAM fabrication. The memory cell and the transistor designs are most important to realize high density, high speed DRAMs. The main features of the technology are a new buried stacked capacitor cell and a high speed CMOS structure. The lithographic levels used were 0.7 µm for critical layers. The technologies have been verified using test vehicles and experimental 16 Mbit DRAM.
Keywords
CMOS technology; Capacitors; DRAM chips; Diodes; Etching; Fabrication; Integrated circuit technology; Leakage current; MOSFETs; Random access memory;
fLanguage
English
Publisher
ieee
Conference_Titel
Electron Devices Meeting, 1987 International
Type
conf
DOI
10.1109/IEDM.1987.191422
Filename
1487380
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