A 4.2 µm2Half-VCCsheath-plate-capacitor DRAM cell with self-aligned buried plate-wiring

A novel trench-capacitor DRAM cell named a half-VCCsheath-plate capacitor (HSPC) cell has been developed by using 0.6µm process technology. It is applicable to DRAMs with capacities of 16M bits and greater. The HSPC cell has achieved a large storage capacitance of 51fF in a small cell area of 4.2µm²and good immunity (critical charge, QC=35fC) against alpha-particle hits. These advantages have been accomplished by using a half-VCCsheath-plane structure, a 5.5nm SiO2-equivalent Si3N4-SiO2composite film, and three self-alignment technologies. These technologies involve buried plate-wiring, sidewall contact, and a pad for the bit-line contact. The device was evaluated using an experimental 2K-bit array.