DocumentCode :
3557083
Title :
Experimental technology and characterization of self-aligned 0.1 µm-gate-length low-temperature operation NMOS devices
Author :
Sai-Halasz, G.A. ; Wordeman, M.R. ; Kern, D.P. ; Ganin, E. ; Rishton, S. ; Ng, H.Y. ; Zicherman, D.S. ; Moy, D. ; Chang, T.H.P. ; Dennard, R.H.
Author_Institution :
IBM T. J. Watson Research Center, Yorktown Heights, N. Y.
fYear :
1987
fDate :
6-9 Dec. 1987
Firstpage :
397
Lastpage :
400
Abstract :
Results are presented from work aimed at demonstrating the feasibility of a Si FET technology in the 0.1µm gate length regime. Self-aligned, n-channel polysilicon gated MOSFETs were designed for optimum operation at cryogenic temperatures (77°K) with reduced power-supply levels. A variety of test chips were assembled and several wafers processed. Direct write electron-beam lithography was used to pattern all levels. The shortest devices fabricated had gate lengths of 70nm. Measured device characteristics yielded over 750mS/mm transconductance.
Keywords :
Assembly; Cryogenics; FETs; Lithography; MOS devices; MOSFETs; Semiconductor device measurement; Temperature; Testing; Transconductance;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices Meeting, 1987 International
Conference_Location :
Washington, DC, USA
Type :
conf
DOI :
10.1109/IEDM.1987.191441
Filename :
1487399
Link To Document :
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