A 1M SRAM with full CMOS cells fabricated in a 0.7 µm technology

A high performance CMOS technology has been developed for application in very fast circuits. A 1 Mb SRAM with 6 transistor cells was designed /1/ end processed. Figure 1 shows a photograph of the completed chip. The insert is a magnification of the corresponding corner. In table 1 the most important design rules are listed with a summary of the technology and some data of the memory. The technology contains 0. 7 µm lithographic dimensions. Important features are: tight field isolation (1.0 µm) achieved by a special masking and oxidation procedure /2/, twin retrograde wells to provide high parasitic threshold and punch throughout voltages and an extremely small n+ to p+ spacing of 2. 5 µm. Latch-up is sufficiently suppressed by the use of thin p^-/p+ epi material. The gate oxide thickness is 17.5 nm. Both n-channel and p-channel MOSTs contain an LDD structure. A strap technology is used to realize buried contacts and local interconnect. Ti salicide technology and double level metal offer a low resistance interconnect. Planarization is applied throughout the process.