A 60 µm2 SOI CMOS SRAM cell formed by new artificial seed method

A new SOI substrate was formed by using artificial 1 µm × 1 µm seeds, solid phase growth, selective epitaxy and polishing technology. The NMOS and PMOS transistors were formed on the substrate. The electron and hole mobility of these devices were of ∼160 cm²/v.sec and ∼100 cm²/v.sec, respectively. The 21 stages ring oscillator gave ∼130 psec of the delay time per stage and ∼220 fJ power-delay product at Vdd of 5 volt. A 60 µm²CMOS SRAM Cell was formed on this substrate using 1 µm design rule. The basic read/write operations were measured at Vdd of 5 volt.