Extended abstract: evaluation of delay queues for a Ravenscar HW kernel

This extended abstract presents work in progress on the evaluation of four delay queues designed for application tailored Ravenscar hardware real-time kernels. The properties of the different queues and optimizations of them are discussed, both for the formal models and for the actual hardware implementations of the queues. Our study of the queues shows that even though parallelism costs much in terms of chip area, there are system configurations where it is the most space conservative.