• DocumentCode
    3557472
  • Title

    Switching loss optimization of 20V devices integrated in a 0.13 μm CMOS technology for portable applications

  • Author

    Grelu, C. ; Baboux, N. ; Bianchi, R.A. ; Plossu, C.

  • Author_Institution
    STMicroelectronics, Crolles
  • fYear
    2005
  • fDate
    23-26 May 2005
  • Firstpage
    339
  • Lastpage
    342
  • Abstract
    Switching performances of low-cost 20V drift-MOSFETs and diffused-MOSFETs power devices are compared. Thanks to a new dynamic gate capacitance measurement protocol, the average gate capacitance responsible for power losses during fast switching transitions is estimated and the Miller effect contribution is quantified. Optimized drift-MOSFETs with reduced gate length and gate to drain overlap present comparable and even better performances than diffused-MOSFETs. Moreover they present the lowest process over-cost, making them excellent and very competitive candidates for low-cost portable power management applications
  • Keywords
    optimisation; power MOSFET; 0.13 micron; 20 V; CMOS technology; MOSFET optimization; Miller effect contribution; diffused-MOSFET; drift-MOSFET; dynamic gate capacitance measurement protocol; portable applications; power MOSFET; switching loss optimization; CMOS technology; Capacitance measurement; Doping; Energy management; Performance evaluation; Protocols; Semiconductor device modeling; Switching loss; Technology management; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Power Semiconductor Devices and ICs, 2005. Proceedings. ISPSD '05. The 17th International Symposium on
  • Conference_Location
    Santa Barbara, CA
  • Print_ISBN
    0-7803-8890-9
  • Type

    conf

  • DOI
    10.1109/ISPSD.2005.1488020
  • Filename
    1488020