Picture-processing techniques for geometrical tolerance checking of integrated-circuit layouts

The checking of geometrical constraints on integrated-circuit layouts is notoriously slow and costly when carried out purely by software. This paper introduces a new approach, in which layers are converted into digitised pictorial form and processed by simple hardware operating like a computer peripheral. This hardware reports to the computer all cases where constraints may be violated, and these cases are investigated in detail purely by software. The advantage of this approach is the reduction in the total amount of c.p.u. time required for constraint checking.